Resistor Pull-Up
What is a resistor?
This passive element is used as the pull-up load in the simplest NMOS inverter.
What is an enhancement-mode NMOS transistor?
This pull-up transistor type requires gate biasing above threshold to conduct strongly.
What is a depletion-mode NMOS transistor?
This load transistor is normally ON even when VGS = 0.
What is a PMOS transistor?
In CMOS, this transistor type acts as the pull-up network.
What is propagation delay?
This circuit parameter measures how fast an inverter changes state.
What is a slower rise time?
Increasing pull-up resistance causes this effect on rise time.
What is threshold voltage drop?
An enhancement-load inverter often cannot reach a full logic HIGH because of this voltage limitation.
What is resistor-load NMOS?
A depletion-load inverter provides a stronger logic HIGH than this earlier NMOS design.
What is steady state?
CMOS inverters ideally consume almost zero static power in this condition.
What is the voltage transfer characteristic (VTC)?
This graph shows the relationship between VIN and VOUT.
What is ON (conducting)?
Static current flows continuously in a resistor-load inverter whenever the NMOS transistor is in this state.
What is saturation region?
In enhancement-load NMOS logic, the load transistor usually operates in this region.
What is switching speed?
Depletion-mode loads improve this important speed characteristic compared with resistor loads.
What is short-circuit power?
During switching, both PMOS and NMOS briefly conduct, causing this type of power dissipation.
What is fan-out?
This term describes the maximum number of inputs driven by one output.
What is excessive power dissipation?
Making the resistor too small increases static current and this unwanted effect.
What is NMOS logic?
This logic family was widely used before CMOS became dominant in VLSI systems.
What is the source terminal?
The gate of a depletion NMOS pull-up is commonly connected to this terminal.
What is one-half of VDD?
The switching threshold of a symmetric CMOS inverter is ideally near this fraction of VDD.
What is noise margin?
This property indicates how much unwanted voltage variation a gate can tolerate.
What is chip area?
The resistor-load inverter has poor area efficiency because integrated resistors occupy large this
What is HIGH?
Enhancement-load NMOS inverters suffer from reduced noise margins due to weak logic this.
What is negative threshold voltage?
A depletion-mode transistor has this type of threshold voltage.
What is noise immunity?
CMOS technology became dominant because of low static power and high this reliability characteristic.
What is supply voltage (VDD²)?
Dynamic CMOS power is approximately proportional to capacitance, frequency, and this squared quantity.