Set 1
x'y'z'+x'y'z'+x'y'+xy' Simplify
y'
Truth Table is
combinations of input values and outputs
Basic building block of counters and shift registers
Flip Flop or Latch
Which component isnot used in combinational logic circuits?
Binary Adders
Ripple carry adder
T Flip-Flop
Encoders
T Flip-Flop
In Gray coding, the adjacent code values differ by _______
1
No. of NOR gates needed to implement AND gate
3
Register is group of
Flip flop
Gates
Inputs
Outputs
Flip Flop
In verilog, the meaning of the following statement reg[7:0] ex [2:0]
a. 3 elements with 8 bit wide
b. 8 elements with 3 bit wide
c. 2 elements with 7 bit wide
d. 7 elements with 2 bit wide
a. 3 elements with 8 bit wide
Simplify the expression using K-maps: F(A,B,C) = (2,3,4,5,6,7)
A+B
Each term in the standard POS form is called as
Minterm
Maxterm
Dont Care
Literal
Maxterm
If I need a light to turn on when 2 switches are turned on, what gate do I need?
AND
Has output only if both inputs are off or on. If one input is on, there is no output.
XNOR
Which gate is best used in a basic comparator to test equality?
AND
XNOR
XOR
OR
XNOR
The output Q of a JK flip flop is 0. Its output does not change when a clock pulse is applied. The input of JK are respectively
a. X and 0
b. X and 1
c. 0 and X
d. 1 and X
c. 0 and X
For positive level triggered T Flip Flop if Qn = 0 1 0 0 1 and T = 1 0 0 1 1, then when the clock is applied, the output is ……
11010
How many 2 input AND gates would I need to have 1 output with 4 inputs?
3
Identify the gate:
Output is low only when and odd number of inputs are high
XNOR Gate
How many gate inputs are required to realize the POS expressions
A(B+C+D')(B'+C+E')(A+B'+C+E)
10
12
14
15
14
Simplify the expression using K-maps: F(A,B,C) = π(0,2,4,8,10) and dc(1,3,4,5,6,7,12,9)
B+D
How many flip flop are required to build a binary counter to count from 0 to 1023
10
Identify the equations
AB + AC + BC
A ⊕ B ⊕ C
Full Adder :Sum and Carry
74LS32
quad 2 input OR Gate IC
The simplified form of the Boolean expression A+AB+ABC+ABCD+ABCDE+......=
A
1
AB
A+AB
A
Which statement defines the hierarchical structure of a Verilog module?
reg
module
assign
initial
module
The number of select lines required for 8:1 mux is
3