Acronym Attack
Verilog Vitals
Timing & Pipelines
Memory Lane
Versus Mode
100

This type of device is "Field Programmable" and uses a gate array architecture.

What is FPGA?

100

The keyword required at the end of a case statement to prevent an inferred latch if not all cases are covered.  

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100

The formula for Slack.

What is "Slack = Clock Period - Setup - Clock Uncertainty - Path Delay"?

100

This type of memory is One-time programmable with mask.

What is ROM?

100

In this machine model, output depends only on current state.

What is a Moore machine?

200

The specific term for a device that is programmed during the manufacturing process

What is mask-programmable/ASIC?

200

This unwanted storage element is inferred when you forget the "else" clause in combinational logic.

What is a latch?

200

This term describes the delay from input to output, which increases when you add pipeline stages.

What is latency?

200

This memory technology uses fuse links combined with ROM structure and was developed because ROM masks were very expensive.

What is PROM (Programmable ROM)?

200

This subroutine type can include timing delays like posedge and wait, but cannot be synthesized.

What is a task?

300

These gates make up Fash-bases PLDS

What are NAND/NOR?

300

These two SystemVerilog keywords explicitly indicate combinational versus sequential always blocks.

What are always_comb and always_ff?

300

This term describes operations per unit time, which improves when you add pipelining without slowing the clock.

What is throughput?

300

This EEPROM variant has rapid erasure time and comes in NOR or NAND technology.

What is Flash memory?

300

This code generation construct can only be used in concurrent code and cannot appear inside procedural blocks like always statements.

What is a generate statement?

400

In the context of CRC and random number generation, this is what LFSR stands for.

What is Linear Feedback Shift Register?

400

This case statement variant treats 'z' as don't-care and uses '?' symbols in case items.

What is casez?

400

If you have a long combinational path causing a setup violation, this is the primary technique used to fix it without changing the logic function.

What is Pipelining / Register Retiming / Adding FFs?

400

This type of Flash memory uses block write/read, is cheaper per bit, and is used for data storage rather than code execution.

What is NAND Flash?

400

For an XOR-based LFSR, This is the "Forbidden State". (XOR vs. XNOR)

All Zeros state (00...)

500

This Xilinx debug IP allows you to drive or observe internal FPGA signals and stands for Virtual Input/Output.

What is VIO?

500

This causes code to run repeatedly in an infinite loop. It is only useful with a delay or control construct, otherwise will create a zero delay infinite loop that can block time progression in simulation.

What is always?

500

Calculate the maximum frequency given: T_clk-q = 2ns, T_logic = 5ns, T_setup = 1ns.

What is (1 / (2+5+1) = 1/8ns = 125MHz)?

500

This programming technology creates conducting paths by changing insulators to polysilicon and is one-time programmable.

What is anti-fuse?

500

This delay model filters out glitches that are shorter than the propagation delay.

What is inertial delay?

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