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What is a Parallel Adder?
A parallel adder adds multiple bits simultaneously using cascaded full adders.
What is carry propagation delay?
It is the delay caused when the carry output of one stage must propagate to the next stage before the final result is obtained.
What are Generate and Propagate signals in CLA?
What is a Flip-Flop?
A flip-flop is a bistable sequential circuit capable of storing one bit of information.
What is the characteristic of a D Flip-Flop?
The output Q follows the input D at the active clock edge and stores the value until the next clock edge.
What is the function of a T Flip-Flop?
When T=1, the output toggles on every clock pulse. When T=0, the output remains unchanged.
Why is JK Flip-Flop called a Universal Flip-Flop?
It can emulate SR, D, and T flip-flops by appropriate input combinations.
What is a 4×4 Multiplier?
A digital circuit that multiplies two 4-bit numbers and produces an 8-bit product.
What are the three steps involved in multiplication?
What is Parity?
Parity indicates whether the number of 1's in a binary word is even or odd.
What is the purpose of an LFSR?
LFSR (Linear Feedback Shift Register) is used for pseudo-random number generation, cryptography, and error detection
What is the difference between Synchronous and Asynchronous Counters?
What is the role of a Testbench in Verilog?
A testbench provides stimulus to the design under test (DUT) and verifies whether the circuit behaves as expected. It is used only for simulation and is not synthesized into hardware.
What is the difference between Mealy and Moore State Machines?
Mealy Machine:Output depends on present state and input
Moore Machine:Output depends only on present state
What software tools are used in this lab?
Intel Quartus Prime and ModelSim.
What is synthesis?
Converting HDL code into hardware logic gates that can be implemented on an FPGA.
What is simulation?
Verifying the functionality of a design before hardware implementation.
Why do we use a clock divider in FPGA implementations?
FPGA clocks are very fast (e.g., 50 MHz); clock dividers slow them down for visible observation on LEDs.
What is the DE10-Lite board used in the lab?
It is an FPGA development board based on Intel MAX 10 FPGA used for implementing and testing Verilog designs.
What is the difference between wire and reg in Verilog?
What is an always block?
An always block executes repeatedly whenever signals in its sensitivity list change.
What is a sensitivity list?
It specifies signals that trigger execution of an always block.
always @(a,b)
What is the difference between blocking and non-blocking assignments?
What is FPGA configuration?
Loading a synthesized design into FPGA memory so the FPGA performs the intended function.
What is clock skew?
Difference in arrival time of the clock signal at different flip-flops.