Final Exam Review

Number Systems and Arithmetic

100

Convert the decimal number 13 to binary.

1101

200

Convert the binary number 101101 to hexadecimal.

2D

300

Find the 2’s complement representation of -18 using 8 bits.

1110 1110

400

Perform the binary addition:
01101101 + 01011110
Indicate if overflow occurs.

Result: 11001011
Overflow: Yes

500

A signed 8-bit system computes: 01010101 + 01100110.

Calculate the result and indicate if overflow occurs.

Result: 1011 1011
Overflow: Yes

Boolean Algebra

100

Simplify: A + 0

A

200

Identify whether this is SOP or POS:
(A + B)(A + C)

POS

300

Simplify using Boolean algebra:
A·B + A·B'

A

400

Write the canonical SOP expression for a function that is 1 for minterms 1, 3, and 5 (3 variables).

F = A'B'C + A'BC + AB'C

500

Given:
F = (A + B)(A + C)(B + C')

Expand into SOP, then simplify

F = AB + AC + BC'

Karnaugh Maps and Minimization

100

How many cells are in a 4-variable Karnaugh map?

16

200

Define a prime implicant (for SOP)

A largest possible grouping of 1s that cannot be expanded further (largest product term that covers as many minterms as possible).

300

Given a 3-variable K-map with 1s at minterms 1, 3, 5, 7, provide a simplified expression.

C

400

Explain the purpose of don’t care conditions.

They allow flexibility to simplify expressions by treating them as 0 or 1.

500

A 4-variable K-map has a checkerboard pattern of 1s. What function does this represent?

XOR/XNOR-type function

Combinational Circuits and Timing

100

Logic gate that outputs 1 only when inputs are different.

XOR

200

This combinational component selects one of many inputs based on select lines.

Multiplexer

300

Convert F = A·B + C into NAND-only implementation.

F = ( (AB)' · C' )'

400

Define critical path.

The longest delay path through a circuit.

500

A combinational circuit implements the function:
F = A·B + A'·C

Determine if there is a timing hazard, and indicate why if so.

Yes. There is a static-1 hazard since A' will cause a delay.

Sequential Logic and FSM

100

Determine the difference between latch and flip-flop.

flip-flops change only at clock edges

200

Indicate the flip-flop that has Q(next) = D

D flip-flop

300

Indicate the difference between a Mealy and a Moore state machine.

Mealy: output depends on state + input
Moore: output depends only on state

400

This is needed to fully specificy a FSM.

Every state has a defined transition for every input (no missing transitions)

500

The steps to design a FSM (give at least 4).

Define inputs and outputs
Draw state diagram
Create state table
Assign binary codes
Derive excitation equations
Derive output equations