Transceivers, IO, and HPS
This is the first generation of Altera FPGAs to integrate ARM CPU cores.
What is Excalibur?
This is the main FPGA architecture building block for implementing logic function
What is lookup table (LUT)?
These are four main stages of FPGA compilation flow
What are Synthesis, Placement, Routing, and Bitstream generation?
University that developed and published 2012 paper on AlexNet - a deep neural network which is credited with starting deep learning revolution
Which is University of Toronto?
The technique to ensure the user design cannot be read
What is encryption?
This is the first FPGA vendor to harden its DDR Controller and which family.
What is Cyclone-5 of Altera?
First Altera FPGA family to include hardened DSP block
What is Stratix-I
These are two most common Hardware Description Languages (HDLs)
What are Verilog and VHDL
INT8 is a very popular precision used for improving performance and power of AI inference workloads. Intel Agilex-5 FPGA has how many more INT8 multipliers per AI tensor block compared to Agilex-7 DSP.
What is 16 more (or 5 times more)?
This type of attack on an FPGA involves the measuring power consumption or electromagnetic radiation to gain insight into the device's operation and potentially extract sensitive information.
What is side-channel attack?
FPGA companies always advertise the highest data rate for their transceiver interfaces. This is the lowest possible transceiver data rate in Agilex FPGAs?
What is 1Gbps?
This is the most important building block of FPGA fabric architecture but it is never mentioned in FPGA datasheets
What is FPGA routing block (RT)
Approximate runtime to compile 1M ALM design
Is it 8-16 hours?
This is Intel primary toolkit for facilitating the optimization of a deep learnings models for Intel hardware.
What is OpenVINO?
I am a cloud computing methodology to remove the CSP from the trust of the tenant
What is confidential Compute?
This is the number of different types of transceiver tiles which are supported by Agilex-7 FPGAs.
What are E-/P-/F-/R-tiles?
These are all types of user-visible on-chip memory in Intel Agilex FPGAs
What are LUTRAM, M20k, and eSRAM?
Estimated codebase size of modern FPGA compilers (Intel Quartus and AMD Vitis)
20-30 million LOCs
The size of original AlexNet network was about 62MB (assuming INT8 precision), which could easily fit on a modern high-end FPGA. This is the current estimates for the latest GPT4 network from OpenAI (order of magnitude).
What is 1.76TB?
This type of attack on an FPGA involves the insertion of malicious logic into the design, often with the intent to compromise the system's functionality or integrity.
What is a Hardware Trojan or Trojan Insertion?
This is the first product that used a hardened NIOS. (Hint: was not in SDM)
What is Arria-10 for transceiver calibration?
What is 16-32
How much faster is Agilex over Stratix-10 in the latest Quartus version (v22.3)
How much is 57.2%?
Google Deepmind did NOT develop a bot for which game: Go, Chess, Starcraft 2, DOTA 2
What is StarCraft2?
Fundamental property of FPGA which can make it more attractive than ASIC from security perspective
Is it losing functionality and bitstream programming when power is cut?