What is Random Access Memory?
RAM is volatile memory that temporarily stores data the CPU is using. It loses all data when the power is off.
List the four stages of the machine instruction cycle
Fetch, decode, execute, store
Allows multiple people to work on the data at the same type
Network Attached Storage (NAS)
Name 3 differences between RAM and ROM
RAM is volatile, used for temporary data, and can be written to. ROM is non-volatile, stores permanent data, and can't be easily modified.
Match each register to its primary role in the cycle: PC, CIR/IR, MBR/MDR, ACC. (One register may match more than one stage.)
Fetch → PC, MBR/MDR
Decode → CIR/IR
Execute → ACC (sometimes MBR/MDR as well if data is fetched)
Store → MBR/MDR, ACC (depending on result destination)
2 of the smallest external storage types
Memory Cards/Flash Drives
What is the difference between terms "cache hit" and "cache miss"?
A cache hit happens when the CPU finds the needed data in the cache, making access faster. A cache miss occurs when the data isn't in the cache, so it must be fetched from slower memory like RAM.
During the fetch stage, which bus carries (a) the address, (b) the instruction word, and (c) the control signal—and which component places each value on the bus? (Address/Data/Control + CPU/memory).
a) PC → MAR — put the next instruction’s address on MAR to drive the address bus.
b)Control unit asserts Memory Read — tells memory to place the instruction word onto the data bus.
c) MDR → CIR — latch the fetched instruction into the IR for decoding.
d) PC ← PC + 1 — advance PC to the address of the following instruction.
Relationship between the Price/Capacity/Speed of all secondary memory types
Generally: As speed increases, capacity decreases, price increases
What is cache and it's purpose? Also explain it's 3 levels
Cache is a small, high-speed memory located close to the CPU that stores frequently used data to speed up processing.
It has three levels:
1) L1 Cache is the smallest and fastest, built directly into the CPU.
2) L2 Cache is larger but slightly slower, often on the CPU chip.
3) L3 Cache is shared between cores, larger and slower than L1 and L2, but still faster than RAM.
Put these steps in the correct order for fetching the next instruction:
(a) Memory places the instruction word on the data bus
(b) PC value is copied to MAR
(c) Control unit asserts Memory Read
(d) MDR copies into CIR (IR)
(e) PC increments to the next address
b → c → a → d → e
Advantages of eMM
Low power consumption, small form factor, inexpensive.
Name all categories of registers with their purposes
General-Purpose Registers:
Used to store temporary data and intermediate results during processing.
Special-Purpose Registers:
Hold specific data like the Program Counter (next instruction address) and the Instruction Register (current instruction).
Control and Memory Interface Registers:
Manage control signals and interface with memory, such as Status Registers (flags) and Memory Address Registers.
In plain language, explain how a STORE instruction writes a value from a CPU register to memory. Name:
1) which register provides the address,
2) which register holds the data,
3)what control signal is used, and
4) the direction of flow on the data bus
Address: Operand address goes into MAR (from the instruction/CIR).
Data: The value to be written is copied from the source register (e.g., ACC/R2) into MDR.
Control signal: Control unit asserts Memory Write on the control bus.
Data bus direction: CPU → memory (MDR drives the data bus; memory latches it at the MAR address).
1. A photographer looking for a storage to save his photos and upload them onto a laptop
2. A team of designers trying to collaborate together
3. An average person looking to save his files (CVs, Gift Card, Photos) on his computer
1. Memory Card
2. NAS
3. SSD/HDD