Flip-Flop Fundamentals
This type of multivibrator has two stable states and stores one bit of information.
What is a bistable multivibrator (flip-flop)?
This type of flip-flop changes state only at the instant of a clock transition.
What is an edge-triggered flip-flop?
This table specifies the required inputs of a flip-flop to achieve a desired state transition.
What is an excitation table?
This unwanted condition occurs in a JK flip-flop when J = K = 1 and the clock pulse width is greater than the propagation delay.
What is the race-around condition?
To design a divide-by-2 frequency divider using a JK flip-flop, both inputs must be tied to this logic level.
What is logic 1 (J = K = 1)?
This flip-flop has two inputs labeled S and R.
What is an SR flip-flop?
A clock that causes state change when it transitions from 0 to 1 is called this type of edge.
What is a positive (rising) edge?
To convert one type of flip-flop into another, this tool is commonly used to simplify the required input expressions.
What is a Karnaugh Map (K-map)?
During race-around, the output toggles repeatedly within one clock pulse because of this parameter being too small.
What is propagation delay?
A 3-bit ripple counter requires this number of flip-flops.
What is 3 flip-flops?
In an SR flip-flop, when S = 1 and R = 0, the output Q becomes this.
What is Set (Q = 1)?
Unlike edge-triggered devices, this type of flip-flop responds for the entire duration that the clock signal is active.
What is a level-triggered flip-flop?
To convert a JK flip-flop into a D flip-flop, both J and K inputs must be expressed in terms of this variable.
What is the D input (desired next state)?
Race-around occurs specifically in this type of flip-flop when both inputs are HIGH.
What is a JK flip-flop?
To design a mod-5 synchronous counter, the minimum number of flip-flops required is this value.
What is 3 flip-flops?
(Since 22<5≤232^2 < 5 \le 2^322<5≤23)
This condition in an SR flip-flop occurs when both inputs are 1, leading to an undefined output.
What is the invalid (forbidden) condition?
This minimum time before the clock edge that the input must remain stable is called this.
What is setup time?
A T flip-flop can be obtained from a JK flip-flop by making these two inputs equal.
What is J = K?
One simple way to prevent race-around is to ensure that the clock pulse width is less than this value.
What is the propagation delay of the flip-flop?
When designing a sequence detector using flip-flops, this diagram is constructed first to represent state transitions.
What is a state diagram?
This flip-flop eliminates the invalid condition of the SR flip-flop by using feedback.
What is a JK flip-flop?
This minimum time after the clock edge that the input must remain stable is known as this.
What is hold time?
To convert a D flip-flop into a T flip-flop, the required input equation is T equal to this expression involving present and next states.
What is T = Q ⊕ Q(n+1)?
(or equivalently T = D ⊕ Q)
This flip-flop configuration uses two stages controlled by complementary clock signals to eliminate race-around.
What is a master-slave flip-flop?
After forming the state table in sequential circuit design, this table is derived to determine required flip-flop inputs.
What is the excitation table?