MOS Transistor
VLSI technology uses ________ to form integrated circuit.
a) transistors
b) switches
c) diodes
d) buffers
Answer: a
Explanation: Very large scale integration is the process of creating an integrated circuit with thousands of transistors into one single chip.
6. ______ architecture is used to design VLSI.
a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit
Answer: c
Explanation: SoC that is system on a chip architecture is used to design the very high level integrated circuit.
11. Which is the high level representation of VLSI design?
a) problem statement
b) logic design
c) HDL program
d) functional design
Answer: a
Explanation: Problem statement is a high level representation of the system. Performance, functionality and physical dimensions are considered here.
4. The photoresist layer is exposed to ____________
a) Visible light
b) Ultraviolet light
c) Infra red light
d) LED
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.
2. Medium scale integration has ____________
a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates
Answer: c
Explanation: Small scale integration has one or more logic gate. Further improved technology is medium scale integration which consists of hundred logic gates. Large scale integration has thousand logic gates.
What is the design flow of VLSI system?
i. architecture design ii. market requirement
iii. logic design iv. HDL coding
a) ii-i-iii-iv
b) iv-i-iii-ii
c) iii-ii-i-iv
d) i-ii-iii-iv
Answer: a
Explanation: The order of the design flow of VLSI circuit is market requirement, architecture design, logic design, HDL coding and then verification.
12. Gate minimization technique is used to simplify the logic.
a) true
b) false
Answer: a
Explanation: Gate minimization technique is used to find the simplest, smallest and effective implementation of the logic.
In nMOS device, gate material could be ____________
a) silicon
b) polysilicon
c) boron
d) phosphorus
Answer: b
Explanation: In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.
3. The difficulty in achieving high doping concentration leads to ____________
a) error in concentration
b) error in variation
c) error in doping
d) distribution error
Answer: b
Explanation: As photolithography comes closer to the fundamental law of optics, achieving high accuracy in doping concentration becomes difficult, which leads to error due to variation.
8. ______ is used in logic design of VLSI.
a) LIFO
b) FIFO
c) FILO
d) LILO
Answer: b
Explanation: First in first out (FIFO) technique and finite state machine technique is used in the logic design of the VLSI circuits.
1. nMOS fabrication process is carried out in ____________
a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals
Answer: a
Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high purity.
6. Which is the commonly used bulk substrate in nMOS fabrication?
a) silicon crystal
b) silicon-on-sapphire
c) phosphorus
d) silicon-di-oxide
Answer: c
Explanation: In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-on-sapphire.
4. _________ is used to deal with effect of variation.
a) chip level technique
b) logic level technique
c) switch level technique
d) system level technique
Answer: d
Explanation: Designers must simulate multiple fabrication process or use system level technique for dealing with effects of variation.
9. Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic
Answer: c
Explanation: Transistor-transistor logic offers higher integration density and it became the first integrated circuit revolution.
2. ______________ impurities are added to the wafer of the crystal.
a) n impurities
b) p impurities
c) siicon
d) crystal
Answer: b
Explanation: p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.
7. In nMOS fabrication, etching is done using ____________
a) plasma
b) hydrochloric acid
c) sulphuric acid
d) sodium chloride
Answer: a
Explanation: In nMOS fabrication, etching is done using hydrofluoric acid or plasma. Etching is a process used to remove layers from the surface.
As die size shrinks, the complexity of making the photomasks ____________
a) increases
b) decreases
c) remains the same
d) cannot be determined
Answer: a
Explanation: As the die size shrinks due to scaling, the number of die per wafer increases and the complexity of making the photomasks increases rapidly.
10. Physical and electrical specification is given in ____________
a) architectural design
b) logic design
c) system design
d) functional design
Answer: d
Explanation: Functional design defines the major functional units of the system, interconnections, physical and electrical specifications.
3. What kind of substrate is provided above the barrier to dopants?
a) insulating
b) conducting
c) silicon
d) semiconducting
Answer: a
Explanation: Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.
8. Heavily doped polysilicon is deposited using ____________
a) chemical vapour decomposition
b) chemical vapour deposition
c) chemical deposition
d) dry deposition
Answer: b
Explanation: The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition.