Introduction to Computer Organization
This principle of von Neumann architecture states that data and instructions are stored in a single read-write memory.
What is Data and instructions stored in single read-write memory?
This component of the memory module divides memory into words, each with a unique address.
What is Word organization and addressing?
This feature of point-to-point interconnects reduces delays by eliminating the need to acquire a shared bus.
What is Lower latency?
This component of PCI Express connects the processor/memory to the PCI Express fabric.
What is Root complex?
This component of basic computer components fetches instructions, decodes them, performs operations, and controls operation.
What is CPU (processor)?
This module, similar to memory, can read data from and write data to I/O ports.
What is I/O Module?
This Intel interconnect uses multiple lanes for data transmission and implements a credit scheme for flow control.
What is Intel QuickPath Interconnect (QPI)?
This layer of PCI Express is responsible for encoding data to allow receiver synchronization.
What is 128b/130b encoding?
This type of program is implemented directly in hardware circuitry and is inflexible, designed for specific computation.
What are Hardwired programs (logic components)?
This set of lines on a bus is used to specify memory address for data transfer.
What is Address bus?
This advantage of point-to-point interconnects enables higher throughput.
What is Higher data rates?
This layer of PCI Express regulates transmission rate across links.
What is Flow control?
This cycle involves the processor fetching an instruction from memory into the instruction register (IR).
What is the Fetch cycle?
This module fetches instructions and data from memory and writes results.
What is Processor Module?
This layer of PCI Express is responsible for managing multiple PCI Express streams.
What are Switches?
This component of PCI Express is responsible for managing external I/O devices.
What are Endpoints?
This allows external devices to interrupt normal program execution, improving processing efficiency.
What are Interrupts?
This shared communication channel allows only one device to use it at a time.
What is Bus as a shared transmission medium?
This protocol layer of QPI handles cache coherency across multiple caches.
What is Protocol Layer?
This feature of PCI Express separates request and completion packets.
What is Split transactions?