This is what FPGA stands for
What is Field Programmable Gate Array?
This is what ASIC stands for
What is Applicable Specific Integrated Circuit?
This the number of times fuses ban be programmed
What is one time?
This signal type can replace wire and reg in system Verilog
What is logic
This is a (blank) type of statement:
sigq <= sigd;
What is non-blocking?
These are 2 applications of FPGAs
What is…
- Glue Logic, Integration(replace smaller devices on a circuit board), ASIC Replacement/Prototype
This is what SWaPC stands for
What is Size, Weight, Power, and Cost?
This PLD is erased using UV light
What is EPROM?
This is the keyword to start a procedural statement for combinatorial logic
This is used to denote code that is executed once at the beginning of the simulation
What is initial ?
These are components that make up programmable logic blocks (PLBs)
What are LUT, reg, and mux?
These are 3 advantages of ASIC over FPGA
What are…
- lower cost at high volume, more area efficient, less/lower power, capable of more complex designs
This PLD has a Programmable AND and FIXED OR (hint: better performance, uses fuse/anti-fuse)
What is PAL?
These are the 5 signal types in System Verilog
what are…
int, real, reg, wire, and logic
These are similar to tasks but are meant to return a value
What is a function?
These are two advantages of SRAM-based FPGAs over Antifuse Programming
What is…
-fast reprogramming, uses latest CMOS technology, majority of FPGAs are SRAM-based
There are arrays of these inside prefabricated silicon chips
What are basic cells?
These are the two volatile PLDS
What are…
- SRAM and CPLD
For this type of procedure statement it is recommended to use non blocking statements
What is Sequential Logic/ code?
This case type treats both x and z as don’t cares
What is casex?
This is the structure in an FPGA defined as 2 logic cells
What is a slice?
This is why ASIC gate arrays were cost-saving
These are the logic gates that make up Flash-based PLDs
What are…
NAND and NOR
This is the conversion of 8’hA5 to decimal
What is 165?
This combination of Blocking/Non-blocking and Delayed Assignment/ Evaluation leads to the same signal but delayed by a specified amount
what is Non-blocking, delayed assignment?