FPGA
ASIC
PLD
Verilog Structure
Verilog Coding
100

This is what FPGA stands for

What is Field Programmable Gate Array?

100

This is what ASIC stands for

What is Applicable Specific Integrated Circuit?

100

This the number of times fuses ban be programmed 

What is one time?

100

This signal type can replace wire and reg in system Verilog 

What is logic

100

This is a (blank) type of statement:

sigq <= sigd;

What is non-blocking?

200

These are 2 applications of FPGAs

What is…

- Glue Logic, Integration(replace smaller devices on a circuit board), ASIC Replacement/Prototype

200

This is what SWaPC stands for

What is Size, Weight, Power, and Cost?

200

This PLD is erased using UV light

What is EPROM?

200

This is the keyword to start a procedural statement for combinatorial logic

what is always_comb?
200

This is used to denote code that is executed once at the beginning of the simulation 

What is initial ?

300

These are components that make up programmable logic blocks (PLBs)

What are LUT, reg, and mux?

300

These are 3 advantages of ASIC over FPGA

What are…

- lower cost at high volume, more area efficient, less/lower power, capable of more complex designs 

300

This PLD has a Programmable AND and FIXED OR (hint: better performance, uses fuse/anti-fuse)

What is PAL?

300

These are the 5 signal types in System Verilog

what are…

int, real, reg, wire, and logic

300

These are similar to tasks but are meant to return a value 

What is a function?

400

These are two advantages of SRAM-based FPGAs over Antifuse Programming 

What is…
-fast reprogramming, uses latest CMOS technology, majority of FPGAs are SRAM-based

400

There are arrays of these inside prefabricated silicon chips

What are basic cells?

400

These are the two volatile PLDS

What are…

- SRAM and CPLD

400

For this type of procedure statement it is recommended to use non blocking statements

What is Sequential Logic/ code?

400

This case type treats both x and z as don’t cares

What is casex?

500

This is the structure in an FPGA defined as 2 logic cells

What is a slice?

500

This is why ASIC gate arrays were cost-saving

What is prefabrication?!
500

These are the logic gates that make up Flash-based PLDs

What are…

NAND and NOR

500

This is the conversion of 8’hA5 to decimal

What is 165?

500

This combination of Blocking/Non-blocking and Delayed Assignment/ Evaluation leads to the same signal but delayed by a specified amount

what is Non-blocking, delayed assignment?