Module 1
Pipelining?
STAGES
Caching?
Caching improves CPU performance by storing frequently accessed data closer to the processor, reducing the need to fetch it from slower memory locations.
Registers?
Data
ALU?
ARITHEMATIC & LOGICAL UNIT
MIPS?
Instruction
Bus?
COMMUNICATION
CACHE?
FASTEST MEMORY
Pipeline?
EFFICIENCY
Encoding?
REPRESENTATION
RISC?
SIMPLICITY
Parallelism?
EFFICIENCY
Endianness?
BYTE
Synchronization?
TIMING
Addressing?
LOCATION
INSTRUCTION?
OPERATION
FLIP FLOPS?
SPECIAL PURPOSE REGISTERS / CONDITIONAL CODES