Sequential Logic
System Verilog
FSMs
Sequential Circuits
Random
100

This type of circuit depends on both current inputs and past history (stored state)

Sequential circuit

100

This block is used to describe combinational logic and automatically infers sensitivity lists.

always_comb

100

This diagram uses circles for states and arrows for transitions to represent system behavior.

FSM diagram

100

This signal enables a register or counter to update its value only when it is active, effectively controlling when state changes occur.

enable

100
How many continents are there

7

200

This distinguishes circuits that update only on clock edges versus those that respond immediately to input changes.

Synchronous and asynchronous
200

This block is specifically used for sequential logic triggered by clock edges.

always_ff

200

In this type of FSM, outputs depend on both current state and inputs.

Mealy machine

200

This input on many counters or registers allows the circuit to be set back to a known initial state, often all zeros.

reset/clear

200

The second planet from the sun

Venus

300

This basic memory element has two inputs labeled S and R and can store one bit.

SR latch

300

This symbol is used to assign a value in a continuous assignment statement.

=

300

In this type of FSM, outputs depend only on the current state.

Moore machine

300

This circuit advances through a predefined sequence of states, often used for counting events.

counter

300

What year did WWI end?

1918

400

These tables specify the required inputs to move a flip-flop from a present state to a desired next state.

excitation tables 

400

This keyword is used to declare a hardware module in SystemVerilog.

module

400

This step in FSM design converts symbolic states into binary values so they can be implemented using flip-flops.

binary encoding

400

This sequential circuit shifts stored data left or right on each clock pulse.

shift-register

400

Koalas are classified under this infraclass

Marsupial

500

This type of flip-flop captures the input value only at a specific clock transition

edge-triggered D flip-flop

500

This data type is commonly used to represent a single binary value (0 or 1) in SystemVerilog.

logic

500

A fully specified FSM must define this for every state and every possible input combination.

transitions and outputs

500

Designing a counter typically requires determining flip-flop inputs using these, derived from desired state transitions.

excitation tables

500
Einstein won a Nobel Prize in physics for this discovery
The photoelectric effect