Boolean Algebra & Logic Gates
Truth Tables
Need for HDL
Gate-Level Modeling in Verilog
Number Systems & Binary Basics
100

What does an AND gate output when both inputs are 1?

1

100

How many rows does a truth table have for a gate with 2 inputs?

4

100

HDL stands for:

Hardware Description Language  

100

In Verilog gate-level modeling, you directly instantiate:

Logic gates (and, or, not, etc.)

100

What is the decimal value of the binary number 1010?

10

200

Which logic gate is known as the "universal gate" because any other gate can be built from it?

NAND

200

How many rows does a truth table have for a circuit with 3 inputs?

8

200

Which HDL will be used throughout this course?

Verilog  

200

A testbench in Verilog is used to:

Apply inputs and check/verify a module's outputs  

200

How many bits are needed to represent the decimal number 15 in binary?

4

300

What is the correct Boolean expression for the OR operation of A and B?

A + B

300

The main purpose of a truth table is to:

List every possible input-output combination

300

A key reason designers use HDL instead of drawing manual schematics is that it:

Scales better for large, complex circuit designs  

300

Which keyword is used to declare a design unit in Verilog?

module  

300

Which number system uses base 16?

Hexadecimal

400

De Morgan's Theorem states that NOT(A AND B) is equal to:

NOT A OR NOT B

400

How many rows are in a NOT gate's truth table?

2

400

Running a design through an HDL simulator before building real hardware helps you:

Verify circuit behavior before hardware implementation  

400

Structural modeling describes a circuit by:

Connecting instances of gates/modules together  

400

What is the binary equivalent of the hexadecimal digit "A"?

1010  

500

An XOR gate outputs a 1 when:

The inputs are different

500

A gate whose truth table reads 00→1, 01→1, 10→1, 11→0 is a:

NAND gate

500

EDA Playground, which we will use this semester, is best described as:

An online Verilog compiler/simulator IDE

500

A Verilog module's inputs and outputs are declared using the keywords:

input / output  

500

In an 8-bit binary number, the leftmost bit is commonly called the:

Most Significant Bit (MSB)