VIRTUAL MEMORY
What is the x86-64 page size? List all that apply.
*This is a preview of our next unit. The most common x86-64 cache line size is 64 bytes. The word size is 8 bytes.
#1, #2, #4. The most common x86-64 cache line size is 64 = 26 bytes, and 26Ă—26 = 212, but there may have been some x86-64 processors with 128-byte cache lines. The word size is 8; 256Ă—8 = 2048, not 4096. There are 8 bits per byte; 216/8 = 213, not 212.
True or false: Given this implementation, a single WeensyOS process can cause the kernel to crash simply by calling share one or more times (with no process ever calling attach). If true, give an example of a call or calls that would likely crash the kernel.
False
What is the x86-64 word size in bits?
64. Registers are 64 bits wide.
What is the maximum size (in pages) of an x86-64 page table (page tables only, not destination pages)? You may write an expression rather than a number.
1 level-4 page table page + 512 level-3 page table pages + 512 * 512 level-2 page table pages + 512 * 512 * 512 level-1 page table pages ----------------------- 2^27 + 2^18 + 2^9 + 1 = 0x8040201 = 134480385 page table pages
True or false: Given this implementation, a single WeensyOS process can cause the kernel to crash simply by calling attach one or more times (with no process ever calling share). If true, give an example of a call or calls that would likely crash the kernel.
True. If the user supplies an out-of-range process ID argument, the kernel will try to read out of bounds of the processes array. Example call: attach(0x1000000, 0, 0).
What kind of address is stored in x86-64 register %rip, virtual or physical?
Virtual. All addresses interpreted by the CPU are virtual except %cr3.
What is the minimum size (in pages) of an x86-64 page table that would allow a process to access 2^21 distinct physical addresses?
4 is a good answer—x86-64 page tables have four levels—but the best answer is one.
Whaaat?! Consider a level-4 page table whose first entry refers to the level-4 page table page itself, and the other entries referred to different pages. Like this:
Physical addressIndexContents0x100000x10070x100810x20070x101020x30070x101830x4007………0x1ff85110x200007
With this page table in force, the 221 virtual addresses 0x0 through 0x1FFFFF access the 221 distinct physical addresses 0x1000 through 0x200FFF.
True or false: Given this implementation, WeensyOS processes 2 and 3 could work together to obtain write access to the kernel code located at address KERNEL_START_ADDR. If true, give an example of calls that would obtain this access.
True, since the attach and share code don’t check whether the user process is allowed to access its memory. An example:
#2: share(3, KERNEL_START_ADDR) #3: attach(2, KERNEL_START_ADDR, 0x110000)
What kind of address is stored in an x86-64 page table entry, virtual or physical?
Physical, for the same reason as in 8A: addresses used to perform virtual-to-physical translations must be physical.
Which of these two machines would support a higher number of concurrent processes without performance problems?
#1 x86-32 with PAE. Each concurrent process occupies some space in physical memory, and #1 has more physical memory.
(Real operating systems swap, so either machine could support more processes than fit in virtual memory, but this would cause thrashing. #1 supports more processes before it starts thrashing.)
True or false: Given this implementation, WeensyOS processes 2 and 3 could work together to obtain write access to any memory, without crashing or modifying kernel code or data. If true, give an example of calls that would obtain access to a page mapped at address 0x110000 in process 5.
The best answer here is false. Processes are able to gain access to any page mapped in one of their page tables. But it’s not clear whether 5’s 0x110000 is mapped in either of the current process’s page tables. Now, 2 and 3 could first read the processes array (via share/attach) to find the physical address of 5’s page table; then, if 2 and 3 are in luck and the page table itself is mapped in their page table, they could read that page table to find the physical address of 0x110000; and then, if 2 and 3 are in luck again, map that page using the VA accessible in one of their page tables (which would differ from 0x110000). But that might not work.
What kind of address is stored in x86-64 register %cr3, virtual or physical?
Physical. Since %cr3 is used by the processor as the base of all virtual-to-physical address translation, it must be a physical address.
Which of these two machines would support a higher maximum number of threads per process? (This is also a preview of a future unit - make an educated guess for now!)
#2 x86-64. Each thread in a process needs some address space for its stack, and an x86-64 process address space is much bigger than an x86-32’s.
True or false: Given this implementation, WeensyOS child processes 2 and 3 could work together to modify the code run by a their shared parent, process 1, without crashing or modifying kernel code or data. If true, give an example of calls that would obtain write access to process 1’s code, which is mapped at address PROC_START_ADDR.
True; since process code is shared after step 7, the children can map their own code read/write, and this is the same code as the parent’s.
#2: share(3, PROC_START_ADDR) #3: attach(2, PROC_START_ADDR, PROC_START_ADDR)
Describe contents of x86-64 physical memory that would ensure virtual addresses 0x10'0ff3 through 0x10'11f2 map to a contiguous range of 512 physical addresses 0x9'9999'9ff3 through 0x9'9999'a1f2. We’ve given you the contents of 2 words of physical memory; you should list more. Assume and/or recall:
Physical address ⟶ Content 0x1f000 ⟶ 0x202007 0x20000 ⟶ 0x1f007
For some 0xWXYZ, you need:
0x202000 ⟶ 0xWXYZ007
0xWXYZ800 ⟶ 0x9'9999'9007
0xWXYZ808 ⟶ 0x9'9999'A007
Why? Well, assume 0xWXYZ = 0x1000.