The Brain
Total Recall
The Cycle
Logic & Gates
Layers & Language
100

Outline the architecture of the central processing unit (CPU).

The CPU consists of the Arithmetic Logic Unit (ALU), the Control Unit (CU), and various registers. 

The ALU handles calculations, the CU manages the flow of data, and registers provide high-speed internal storage for immediate operations.

100

Distinguish between RAM and ROM.

RAM is volatile and used for running programs/data; ROM is non-volatile and used for permanent instructions like the BIOS.

100

List the four stages of the machine instruction cycle.

Fetch, Decode, Execute, and Store.

100

Define the three basic logic gates used in DP Computer Science.

AND, OR, and NOT.

100

Define the "Operating System" (OS).

Software that manages computer hardware/software resources and provides common services for computer programs.

200

What are the specific functions of the ALU and the Control Unit?

The ALU performs all arithmetic (+, -) and logical (AND, OR) operations; the CU decodes instructions and controls the fetch-execute cycle.

200

Explain the use of cache memory.

It is high-speed memory between the CPU and RAM that stores frequently used data to speed up processing.

200

What happens during the "Decode" stage of the cycle?

The Control Unit (CU) interprets the instruction held in the Instruction Register to determine what action is required.

200

Construct a truth table for an "XOR" gate.

Output is 1 only if inputs are different (0,1 or 1,0); otherwise, it is 0.

200

Identify two resources the OS must manage.

Memory, Peripherals, Processor time, or Storage.

300

Identify the two registers students are required to include in a block diagram of the CPU.

The Memory Address Register (MAR) and the Memory Data Register (MDR).

The MAR holds the address of the data to be fetched, while the MDR holds the actual data being transferred to or from memory.  

300

Define the term "Primary Memory."

Memory that is directly accessible by the CPU, primarily consisting of RAM and ROM.

300

Where does the CPU "Store" the result after the "Execute" phase?

Results are stored back in the registers or primary memory (RAM).

300

What is the output of a NAND gate if both inputs are 1?

0 (False) 


NAND is the inverse of AND; since AND(1,1) is 1, NAND(1,1) is 0.

300

What is the purpose of "Virtual Memory" in an OS?

To allow the execution of processes that are larger than the available physical RAM by using secondary storage.

400

Explain the relationship between the MAR and the MDR during a "fetch" operation.

The CU places the address in the MAR; the data at that address is then copied from RAM into the MDR.

400

Explain the need for persistent storage (Secondary Memory).

To store data and programs permanently when the power is turned off (non-volatile storage).

400

How does the "Fetch" stage utilize the Data Bus?

The Data Bus carries the actual instruction/data from RAM to the CPU's MDR.

400

Describe the purpose of a truth table in circuit design.

To show all possible input combinations and their resulting outputs for a logic circuit.

400

List two common software applications.

Word processors, Spreadsheets, DBMS, Web browsers, Email clients, or CAD.

500

Describe the primary role of the Control Unit (CU) in the machine instruction cycle.

It coordinates the movement of data by providing timing and control signals to other components.

500

Why is cache memory considered a trade-off in computer design?

It is significantly faster than RAM but much more expensive and has a smaller capacity.

500

Explain how the program counter (PC) facilitates the cycle.

It holds the memory address of the next instruction to be fetched, incrementing after each fetch.

500

Identify the gate that produces a 1 output only if all inputs are 0.

A NOR gate.

500

Outline the function of the "Kernel" in an OS.

The core part of the OS that manages system resources and the communication between hardware and software.