Verilog Basics
Which keyword is used to define a hardware module in Verilog?
module
Which keyword is used to end a Verilog module?
endmodule
What symbol is used for single-line comments in Verilog?
//
Which Verilog construct is mainly used for continuous assignment?
assign
Write the syntax to declare a 4-bit input named A.
input [3:0] A;
Which data type represents physical connections in Verilog?
wire
Which data type stores values inside procedural blocks?
reg
What is the default value of an uninitialized reg variable in simulation?
x (unknown)
Which keyword is used to define an integer variable in Verilog?
integer
How do you declare an 8-bit register named data?
reg [7:0] data;
Which operator is used for logical AND in Verilog?
&&
Which operator is used for bitwise OR?
|
Which operator is used for equality comparison?
==
Which operator performs left shift operation?
<<
What will be the output of the following expression? 4'b1010 & 4'b1100
4'b1000
Which block is generally used for sequential logic?
always
Which edge keyword is used for positive edge triggering?
posedge
Write the sensitivity list for a positive-edge-triggered clock named clk.
always @(posedge clk)
Which assignment operator is preferred inside sequential always blocks?
Non-blocking assignment (<=)
What is the main difference between blocking (=) and non-blocking (<=) assignments?
Blocking assignments execute sequentially, while non-blocking assignments execute in parallel at the end of the time step.
Which system task is used to display output on the console?
$display
Which keyword is commonly used to generate simulation delays?
#
Which system task stops the simulation?
$stop
Which system task completely exits the simulation?
$finish
Write a statement to generate a clock that toggles every 5 time units.
always #5 clk = ~clk;