Module 1
Module 2
Module 3
Module 4
Module 5
100

Pipelining?

STAGES

100

Caching?

Caching improves CPU performance by storing frequently accessed data closer to the processor, reducing the need to fetch it from slower memory locations.

100

Registers?

Data

100

ALU?

ARITHEMATIC & LOGICAL UNIT

100

MIPS?

 Instruction

200

Bus?

COMMUNICATION

200

CACHE?

FASTEST MEMORY 

200

Pipeline?

EFFICIENCY

200

Encoding?

REPRESENTATION

200

RISC?

SIMPLICITY

300

Parallelism?

EFFICIENCY

300

Endianness?

BYTE

300

 Synchronization?

TIMING 

300

Addressing?

LOCATION

300

INSTRUCTION?

OPERATION

400

FLIP FLOPS?

SPECIAL PURPOSE REGISTERS / CONDITIONAL CODES

M
e
n
u